This invention relates to random access memories (RAM) and more particularly to one in which data words may be stored on and retrieved from bit boundaries.
In data processing systems, most RAMs are organized to store data on word boundaries; and typically data is organized in words for ease of handling, even where system and data packing efficiency is compromised.
However, in many instances such as the processing of serial bit streams in data transmission applications, it is desirable to store the serial data in and retrieve data from a RAM on bit boundaries rather than word boundaries while retaining the parallel storage of a data group of word length.
R. C. Tong (IBM Technical Disclosure Bulletin, Volume 26, No. 12, pages 6473-5, published May, 1984) illustrates and describes a memory with bit boundary accessing using a shift register and row select lines. However, his article suggests two memory cycles to store into two successive odd-even words of memory.
U.S. Pat. No. 4,520,439, issued May 28, 1985 to A. E. Liepa, shows means for storing data on bit boundaries in a word oriented RAM; however it requires reading existing data from two adjacent words, merging new data with the existing data (which is not to be modified) in logic external to the memory and storing the merged data back in memory.
U.S. Pat. No. 4,099,253 issued Jul. 4, 1978 to P. G. Dolley, Jr. show a memory constructed of a plurality of semiconductor chips, each capable of storing one bit at each of a plurality (2.sup.N) of locations addressed through N address terminals. By chip selection signals, the chips may be accessed alternatively in parallel to read/write multibit words or individually to read/ write a single bit.
The above and other known prior art, do not show a RAM arrangement in which, during one memory cycle, a complete word may be written into/retrieved from one word location or two adjacent word locations on any selected bit boundary, wherein the RAM is of a conventional type in which the word address decode mechanism is implemented within the chip containing the storage bit cells.
It is therefore a primary object of the present invention to provide an improved memory in which a data word may be stored into/retrieved from one word location or two adjacent word locations on any bit boundary during one memory cycle.